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1 tm file number 3127.5 hi-5042, hi-5043, HI-5047, hi-5049, hi-5051 cmos analog switches this family of cmos analog switches offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 80ma. ?on? resistance is low and stays reasonably constant over the full range of operating signal voltage and current. r on remains exceptionally constant for input voltages between +5v and -5v and currents up to 50ma. switch impedance also changes very little over temperature, particularly between 0 o c and 75 o c. r on is nominally 25 ? for hi-5049 and hi-5051 and 50 ? for hi-5042 through HI-5047. all devices provide break-before-make switching and are ttl and cmos compatible for maximum application versatility. performance is further enhanced by dielectric isolation processing which insures latch-free operation with very low input and output leakage currents (0.8na at 25 o c). this family of switches also features very low power operation (1.5mw at 25 o c). there are 7 devices in this switch series which are differentiated by type of switch action and value of r on (see functional description table). the hi-504x and hi-505x series switches can directly replace ih-5040 series devices, and are functionally compatible with the dg180 and dg190 family. features wide analog signal range . . . . . . . . . . . . . . . . . . . 15v low ?on? resistance . . . . . . . . . . . . . . . . . . . . . . . . . 25 ? high current capability . . . . . . . . . . . . . . . . . . . . . . 80ma break-before-make switching - turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370ns - turn-off time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns no latch-up input mos gates are protected from electrostatic discharge dtl, ttl, cmos, pmos compatible applications high frequency switching sample and hold digital filters operational amplifier gain switching functional diagram ordering information part number temp. range ( o c) package pkg. no. hi1-5042-2 -55 to 125 16 ld cerdip f16.3 hi1-5043-2 -55 to 125 16 ld cerdip f16.3 hi1-5043-5 0 to 75 16 ld cerdip f16.3 hi3-5043-5 0 to 75 16 ld pdip e16.3 hi9p5043-5 0 to 75 16 ld soic m16.15 hi1-5047-5 0 to 75 16 ld cerdip f16.3 hi1-5049-5 0 to 75 16 ld cerdip f16.3 hi1-5051-2 -55 to 125 16 ld cerdip f16.3 hi1-5051-5 0 to 75 16 ld cerdip f16.3 hi3-5051-5 0 to 75 16 ld pdip e16.3 hi9p5051-9 -40 to 85 16 ld soic m16.15 functional description part number type r on hi-5042 spdt 50 ? hi-5043 dual spdt 50 ? HI-5047 4pst 50 ? hi-5049 dual dpst 25 ? hi-5051 dual spdt 25 ? s n a p d data sheet september 2001 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ? intersil americas inc. 2001, all rights reserved
2 pinouts (switches shown for logic ?0? input) single control spdt hi-5042 (50 ? ) 4pst HI-5047 (50 ? ) note: unused pins may be internally connected. ground all unused pins. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v- v+ d 1 d 2 s 2 s 1 a v l v r 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v- v+ d 2 d 1 s 1 s 2 s 4 d 4 d 3 v l v r a s 3 pinouts (switches shown for logic ?0? input) dual control dual spdt hi-5043 (50 ? ), hi-5051 (25 ? ) dual dpst hi-5049 (25 ? ) note: unused pins may be internally connected. ground all unused pins. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 d 3 s 3 s 4 d 4 v- v+ s 1 s 2 a 2 v l v r a 1 d 1 d 2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v- v+ s 1 s 2 a 2 v l v r a 1 d 3 s 3 s 4 d 4 d 1 d 2 switch functions (switches shown for logic ?1? input) spdt hi-5042 (50 ? ) dual spdt hi-5043 (50 ? ) 4pst HI-5047 (50 ? ) dual dpst hi-5049 (25 ? ) dual spdt hi-5051 (25 ? ) 12 11 13 14 15 a 1 16 3 4 v+ v l s 1 s 2 v- v r d 1 d 2 1 3 8 6 5 9 10 12 15 4 16 11 13 14 v+ v l s 1 a 1 a 2 s 4 s 3 s 2 v- v r d 1 d 2 d 4 d 3 12 11 13 14 15 3 4 1 16 8 9 6 5 d 1 d 2 d 4 d 3 s 1 s 3 s 4 s 2 a v- v r v+ v l 1 3 8 6 5 9 10 12 15 4 16 11 13 14 v+ v l s 1 a 1 a 2 s 4 s 3 s 2 v- v r d 1 d 2 d 4 d 3 1 3 8 6 5 9 10 12 15 4 16 11 13 14 d 1 d 2 d 4 d 3 s 1 a 1 a 2 s 4 s 3 s 2 v- v r v+ v l hi-5042 thru hi-5051
3 schematic diagrams note: connect v+ to v l for minimizing power consumption when driving from cmos circuits. ttl /cmos reference circuit (note) switch cell note: all n-channel bodies to v-, all p-channel bodies to v+ except as shown. digital input buffer and level shifter p14 p15 p16 qn1 qp1 25 a p13 v+ qn2 n14 n15 n16 qp2 r7 qp3 qp4 qp5 qp6 qp8 r2 qp7 r4 r5 r6 r3 to v r ? to v l ? v- v+ 25 a 25 a 25 a 100 a 16 a 25 a v l v r 35 a n13 p2 n2 n1 n3 v- p1 in out v+ a 1 (a 2 ) a 1 (a 2 ) n1 n2 p2 p1 p3 p5 p4 p6 p7 p8 p9 p10 p11 p12 a1 a2 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 v- v l ' v r ' v+ v+ d2 d1 v- a r4 200 ? a1 a2 hi-5042 thru hi-5051
4 absolute maximum ratings thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v v r to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+, v- digital and analog input voltage . . . . . . . . . . . . (v+) +4v to (v-) -4v analog current (s to d) continuous . . . . . . . . . . . . . . . . . . . . 30ma analog current (s to d) peak . . . . . . . . . . . . . . . . . . . . . . . . . 80ma operating conditions temperature range hi-50xx-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c hi-50xx-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c hi-50xx-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 75 22 soic package . . . . . . . . . . . . . . . . . . . 110 n/a pdip package . . . . . . . . . . . . . . . . . . . 90 n/a maximum junction temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c ceramic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage temperature. . . . . . . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v r = 0v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v, v l =5v, unless otherwise specified. for test conditions, consult performance characteristics, unused pins are grounded parameter test conditions temp ( o c) -2 -5, -9 units min typ max min typ max dynamic characteristics switch on time, t on (note 5) 25 - 370 500 - 370 500 ns switch off time, t off (note 5) 25 - 280 500 - 280 500 ns charge injection, q (note 3) 25 - 5 20 - 5 - mv off isolation (note 4) 25 75 80 - - 80 - db crosstalk (note 4) 25 -80 -88 - - -88 - db input switch capacitance, c s(off) 25 -11- -11- pf output switch capacitance, c d(off) 25 -11- -11- pf output switch capacitance, c d(on) 25 -22- -22- pf digital input capacitance, c a 25 - 5 - - 5 - pf drain to source capacitance, c ds(off) 25 - 0.5 - - 0.5 - pf digital input characteristics input low threshold, v al full - - 0.8 - - 0.8 v input high threshold, v ah full 2.4 - - 2.4 - - v input leakage current (high or low), i a full - 0.01 1.0 - 0.01 1.0 a analog switch characteristics analog signal range full -15 - +15 -15 - +15 v on resistance, r on hi-5042 to HI-5047 (note 2) 25 - 50 75 - 50 75 ? full - - 150 - - 150 ? hi-5049, hi-5051 (note 2) 25 - 25 45 - 25 45 ? full--50--50 ? channel-to-channel match, ? r on hi-5042 to HI-5047 25 - 2 10 - 2 10 ? hi-5049, hi-5051 25 - 1 5 - 1 5 ? off input or output leakage current, i s(off) = i d(off) 25 - 0.8 2 - 0.8 2 na full - 100 200 - 100 200 na hi-5042 thru hi-5051
5 on leakage current, i d(on) 25 -0.012 -0.012 na full - 2 200 - 2 200 na power requirements quiescent power dissipation, p d 25 - 1.5 - - 1.5 - mw i+, i-, i l , i r 25 - - 0.2 - - 0.3 ma i+, +15v quiescent current (note 5) full - - 0.3 - - 0.5 ma i-, -15v quiescent current (note 5) full - - 0.3 - - 0.5 ma i l , +5v quiescent current (note 5) full - - 0.3 - - 0.5 ma i r , ground quiescent current (note 5) full - - 0.3 - - 0.5 ma notes: 2. v out = 10v, i out = 1ma. 3. v in = 0v, c l = 10nf. 4. r l = 100 ? , f = 100khz, v in = 2.0v p-p , c l = 5pf. 5. v al = 0v, v ah = 5v. electrical specifications supplies = +15v, -15v; v r = 0v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v, v l =5v, unless otherwise specified. for test conditions, consult performance characteristics, unused pins are grounded (continued) parameter test conditions temp ( o c) -2 -5, -9 units min typ max min typ max test circuits and waveforms t a = 25 o c, v+ = +15v, v- = -15v, v l = +5v, v r = 0v, v ah = 3v and v al = 0.8v unless otherwise specified figure 1a. test circuit figure 1b. on resistance vs analog signal level figure 1c. normalized on resistance vs temperature figure 1. on resistance in out 1ma v 2 r on = 1ma v 2 v in analog signal level (v) on resistance ( ? ) 80 60 40 20 0 -15 -10 -5 051015 v+ = +10v v- = -10v v+ = +12v v- = -12v v+ = +15v v- = -15v temperature ( o c) -50 -25 0 75 100 125 50 25 0.6 1.2 1.1 1.0 0.9 0.8 0.7 normalized on resistance (referred to 25 o c) v in = 0v hi-5042 thru hi-5051
6 figure 2a. leakage currents vs temperature figure 2b. test circuits figure 2. leakage currents figure 3a. normalized on resistance vs analog current figure 3b. test circuit figure 3. normalized on resistance figure 4a. off isolation vs frequency figure 4b. test circuit figure 4c. off isolation test circuits and waveforms t a = 25 o c, v+ = +15v, v- = -15v, v l = +5v, v r = 0v, v ah = 3v and v al = 0.8v unless otherwise specified (continued) i d(on) temperature ( o c) 75 100 125 50 25 i s(off) = i d(off) 100na 10na 1na 100pa 10pa leakage current in out a a 10v in out a 10v i d(on) i d(off) i s(off) 10v on leakage current off leakage current analog current (ma) 40 60 80 20 0 1.4 normalized on resistance 1.3 1.2 1.1 1.0 (referred to 1ma) in out v in i r on v in i --------- = frequency (hz) 10k 100k 1m 100 1 200 off isolation (db) 160 120 80 40 1k 10 r l = 100 ? r l = 10k ? 50 ? r l v out v in 2v p-p in out off isolation 20 log v in v out --------------- - ?? ?? ?? = hi-5042 thru hi-5051
7 figure 5a. crosstalk vs frequency figure 5b. test circuit figure 5. crosstalk figure 6a. power consumption vs frequency figure 6b. test circuit figure 6. power consumption figure 7a. test circuit figure 7b. measurement points test circuits and waveforms t a = 25 o c, v+ = +15v, v- = -15v, v l = +5v, v r = 0v, v ah = 3v and v al = 0.8v unless otherwise specified (continued) frequency (hz) -200 -160 -120 -80 -40 10k 100k 1m 100 11k 10 0 crosstalk (db) r l = 100 ? r l = 10k ? r l = 1k ? 50 ? r l r l v out v in 2v p-p switched channel crosstalk 20 log v out v in --------------- - ?? ?? ?? = toggle frequency (50% duty cycle) (hz) 200 160 120 80 40 10k 100k 1m 1k 0 power consumption (mw) v r v l i l v+ v- a i - i + +5v +15v -15v +10v -10v toggle at 50% duty +10v in 1 in 2 v a 1k 1k out 1 out 2 90% 90% t off t on t on t off 90% 90% v a out 1 out 2 v ah hi-5042 thru hi-5051
8 v a = 0v to 5v vertical: 2v/div. horizontal: 200ns/div. figure 7c. waveforms with ttl compatible logic input v a = 0v to 10v vertical: 5v/div. horizontal: 200ns/div. figure 7d. waveforms with cmos compatible logic input figure 7e. switching times vs positive digital voltage figure 7f. switching times vs negative digital voltage figure 7. switch t on and t off test circuits and waveforms t a = 25 o c, v+ = +15v, v- = -15v, v l = +5v, v r = 0v, v ah = 3v and v al = 0.8v unless otherwise specified (continued) v a output v a output digital ?high? (v) 2.4 3.0 3.6 4.2 4.8 720 660 600 540 480 420 360 300 240 180 120 60 t on t off ( need input ) digital ?low? (v) 0 0.5 1.0 1.5 720 660 600 540 480 420 360 300 240 180 120 60 t on t off ( need input ) hi-5042 thru hi-5051
9 hi-5042 thru hi-5051 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
10 hi-5042 thru hi-5051 small outline plastic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93
11 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by int ersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or othe r rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. c - f ramuz 43 ch-1009 pully switzerland tel: +41 21 7293637 fax: +41 21 7293684 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 hi-5042 thru hi-5051 ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f16.3 mil-std-1835 gdip1-t16 (d-2, configuration a) 16 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n16 168 rev. 0 4/94

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